Currently, the global AI chip market is undergoing a profound paradigm shift.
For a long time, GPUs have been regarded as the default option for AI training. However, around 2025, an industrial transformation centered on ASICs began to ferment intensely.
ASIC: Signals and Data of an Industrial Inflection Point
In Q1 2026, Google's TPU share in AI server shipments soared to 78%, far exceeding the GPU share; OpenAI announced plans to deploy Broadcom custom ASICs from the second half of 2026 to 2027 to build a 10-gigawatt computing power cluster, reducing single computing power cost by approximately 35%.
Behind these signals lies a historic shift in the center of gravity of AI computing power, moving from the training arms race to the large-scale deployment of inference.
Meanwhile, MediaTek's Vice Chairman, Tsai Li-hsin, explicitly listed data center ASICs as "the company's most imaginative growth engine" during an earnings call, raising revenue targets and indicating that orders from hyperscale customers are accelerating their implementation.
Qualcomm announced its entry into the data center battlefield. Leveraging the IP accumulated through the acquisition of AlphaWave, it secured key major customers, declaring its determination to challenge NVIDIA head-on.
Domestically, VeriSilicon Microelectronics's ASIC mass production business exploded, while ASR (Awinic) positioned its ASIC customization business as a "second growth curve" for the first time. Both independent IC design service providers have demonstrated high-growth logic in their financial performance.
These densely released signals all point to the same emerging fact: the ASIC industry is ushering in a "golden era." This is not a strategic choice of a few companies but a comprehensive industrial inflection point.
The latest data from Deloitte reveals this inflection point: The proportion of AI inference workloads surged from one-third in 2023 to two-thirds in 2026, and will further increase in the long term, with a market size 2-3 times that of training hardware. Goldman Sachs further predicts that ASICs' share of the AI chip market will rise to 40% in 2026 and exceed 45% in 2027, nearly equal to GPUs. Counterpoint Research notes that the AI ASIC market size will grow from $12 billion in 2024 to $30 billion in 2027, with a CAGR of 34%.
Overall, the AI accelerator market in 2026 is at a critical turning point—competition has expanded from the performance comparison of individual chips to a comprehensive confrontation encompassing interconnects, switches, software ecosystems, and system architectures.
Why Are ASICs Taking Off Now?
If one were to find a fulcrum for the rise of ASICs, the answer might lie in the most fundamental economic equation of the AI industry.
As AI large model optimization drastically reduces inference costs, and AI programming and AI agents widely enter industrial production processes, AI inference exploded in the second half of 2025 and became an industry consensus. A simple physical fact gradually became unavoidable: when model deployment scales to hundreds of millions of users, using expensive general-purpose GPUs costing tens of thousands of dollars for high-concurrency instant inference is essentially "using a sledgehammer to crack a nut"—not impossible, but structurally uneconomical.
This is precisely ASIC's opportunity.
As AI computing demand structurally shifts from training-led to inference-led, the energy efficiency and cost advantages of customized chips become the core driving force. In inference scenarios, ASIC chips offer lower latency, lower energy consumption, and better unit cost, fundamentally shaking the cost model established by GPUs over the past decade.
General-purpose GPUs face dual bottlenecks in power consumption and cost in inference scenarios, a contradiction that becomes increasingly prominent especially when the explosion of AI agents causes Token consumption to surge 10-100 times. ASICs, through customized architectures, dedicate all transistor resources to specific computations, eliminating redundant functions, achieving 3-5 times improvement in energy efficiency, and reducing TCO by 40-60%, perfectly fitting large-scale inference scenarios.
For example, the custom inference chip jointly launched by OpenAI and Broadcom achieved an energy efficiency of 6.8 TOPS/W, while the corresponding metric for NVIDIA's GB200 is only 4.5 TOPS/W—the difference is clear. The new head of Amazon's AI infrastructure once stated frankly: "If we can build models on our own chips, we can complete these tasks at a fraction of the cost of a pure AI model provider."
More importantly, this wave of ASICs is not a disorderly explosion starting from zero, but is built upon a matured consensus on AI workloads.
It is reported that the Transformer architecture has long dominated the large model world, making the specificity of ASIC design no longer trapped by the classic curse of "too narrow application scope"—any specialized architecture highly optimized for Transformers can realize its cost and energy efficiency advantages in a sufficiently broad market space.
Historically, ASICs were long confined to niche scenarios due to "high investment, high risk." Now, this premise has changed: when specialized design faces a servable market worth tens of billions of dollars, and the workload structure is highly unified, ASICs have truly evolved from a low-cost alternative to GPUs to an inevitable option for the evolution of AI infrastructure.
Simultaneously, the collective pivot of major Cloud Service Providers (CSPs) released the most critical market signal.
As the world's largest computing power purchasing group, major CSPs like Google, AWS, Microsoft, and Meta are uniformly tilting towards self-developed or custom ASICs. TrendForce estimates that in 2026, the demand for AI servers from CSPs and sovereign clouds will remain strong, and the shipment growth rate of ASIC servers at 44.6% will significantly surpass that of GPU servers at 16.1%.
This is by no means simply a "cost reduction" mindset—with AI infrastructure becoming a core strategic resource, mastering the definition power of chips means mastering the pricing power of computing and the autonomy of the supply chain. Voting for ASICs with real money has become a strategic necessity for cloud vendors moving from passive procurement to active definition.
Old and New Forces Intertwined, Reshaping the Global ASIC Landscape
Beyond the explosion in demand for AI computing power, another hallmark of the ASIC golden era is—suddenly, there are many more players on the stage.
In the past, the ASIC narrative mainly revolved around two established players, Broadcom and Marvell; today, mobile chip giants like MediaTek and Qualcomm are crossing boundaries and rewriting the ASIC competitive landscape.
MediaTek Scores First, Betting Big on ASICs
MediaTek's transformation story is perhaps the most dramatic sample in this wave of ASICs.
Against the backdrop of the mobile phone market hitting a growth ceiling and gross margins falling to a four-year low of 47.5% in 2025, MediaTek CEO Tsai Li-hsin decisively locked data center ASICs as the company's most imaginative growth engine. During an earnings call last July, he foretold the market that the first ASIC project would be finalized for design that quarter, contributing revenue starting in 2026; by February 2026, Tsai was able to modify his confidence with the word "very"—data center ASIC revenue would absolutely exceed $1 billion in 2026, looking towards tens of billions in 2027.
The speed of achieving this target even exceeded analysts' expectations. According to public reports, MediaTek's successful capture of Google's data center ASIC order is the core result of scoring first in this high-stakes gamble.
Tsai Li-hsin himself gave a remarkable judgment: the global data center ASIC market is expected to reach a scale of $70 billion by 2028, and MediaTek's target is not just the previously estimated 10% to 15% market share—"We will strive for higher." To support this ambition, MediaTek has increased investment in several key technology areas including high-speed 400G SerDes, CPO co-packaged optics, 3.5D advanced packaging, and customized HBM.
Goldman Sachs' latest forecast points out: MediaTek's AI ASIC revenue could reach up to $12.3 billion in 2027, corresponding to a 10-15% market share; by 2028, the AI business proportion will exceed 60% (66%), with AI ASIC revenue scale potentially reaching $48 billion. Counterpoint Research is even more optimistic, expecting MediaTek to capture 26% of the AI ASIC market share by 2028, with shipments growing 10-fold from 2026 to 2028, becoming the world's second-largest supplier, second only to Broadcom.
It can be said that MediaTek is proving with a leap from edge to cloud that the SoC integration capabilities accumulated in the 5G era can also open up vast imagination space in the data center field.
Qualcomm: Late Mover Advantage, Striking at the Core of Inference
If MediaTek is the steady and solid pioneer, then Qualcomm is the aggressive disruptor.
In 2025, Qualcomm fully acquired high-speed wired connectivity technology company AlphaWave Semi for $2.4 billion, completing the transaction in Q1 2026. The intent of this move is extremely clear: to leverage the IP assets accumulated by AlphaWave, fill the critical capability gap in high-performance data center interconnects and custom chip design, paving the way for a large-scale entry into the cloud-side custom chip market.
Qualcomm's approach can be described as swift and fierce.
On April 30, 2026, Qualcomm CEO Cristiano Amon publicly confirmed that the company is collaborating with a leading hyperscale cloud service provider to develop custom chips, with the first shipments scheduled to start in the December quarter, focusing on optimization for AI inference scenarios.
More notable is Qualcomm's "three-pronged" strategy: simultaneous research and development of general-purpose CPUs, accelerators specifically built for AI inference, and fully custom ASIC chips, forming a complete data center solution matrix. It is reported that in October 2025, Qualcomm launched the AI200/AI250 duo for data center inference. AI200 is expected to be commercialized in 2026, and AI250 is planned for 2027. In April 2026, Qualcomm confirmed that the custom ASIC project in collaboration with a leading hyperscale cloud vendor would commence initial shipments within the year.
Against the backdrop of core customers like Apple and Samsung accelerating their self-developed chips and its consumer electronics business facing structural pressure, Qualcomm chose to enter a new battlefield with an estimated market size in the trillions of dollars in this manner. Amon's statement on this is concise and powerful: "We can say we have bottomed out."
Qualcomm's differentiated advantage also lies in the ecosystem integration of edge-cloud synergy. Its ASICs can not only efficiently run cloud inference tasks but also achieve seamless connectivity with Snapdragon mobile platforms and IoT chips, providing customers with a full-stack AI solution from the endpoint to the cloud.
Broadcom and Marvell: The Ace Territory of the Twin Giants
While new forces are advancing triumphantly, the traditional twin giants have not stood still either.
In the ASIC field, Broadcom has long been the recognized overlord.
Thanks to growth in custom chip and AI networking product businesses, Broadcom's revenue rose to $39.7 billion in 2025, a year-on-year increase of 30%. Its financial performance shows that the value center of AI semiconductors has diffused from GPUs to custom AI chips and overall network architecture components like Ethernet switches and NICs.
Broadcom's revenue structure is undergoing a fundamental transformation: in the first quarter of fiscal year 2026, Broadcom's AI-related revenue reached $8.4 billion, a year-on-year increase of 106%, and its proportion of semiconductor revenue continues to climb.
Simultaneously, Broadcom CEO Hock Tan threw out an even more astonishing prediction during the earnings call: by 2027, revenue from AI chips (custom ASICs) alone will exceed $100 billion, with total shipments approaching 10 gigawatts. This target far exceeds previous market expectations.
LLM platform-level companies like Google, Meta, OpenAI, and Anthropic are building their own custom XPUs. Broadcom revealed that it is currently working closely with six major customers to jointly develop AI-specific processors. These customers include:
- Google: An important partner for TPU chips, with order scale continuously expanding
- Meta: Progress on the MTIA series chip roadmap is smooth, with delivery volume reaching several gigawatts in 2027
- Anthropic: Plans to deploy over 3 gigawatts of TPU computing power in 2027
- OpenAI: Announced deployment of the first-generation XPU starting from 2027, with first-year computing capacity exceeding 1 gigawatt
It is worth noting that Broadcom's cooperation with customers is not short-term transactions but multi-generation strategic bindings, with cooperation cycles spanning 2-4 years of rolling planning. A Broadcom executive's statement on this is quite telling: "These are all real customer demands, and the business scale will continue to grow."
On the other side, Marvell's layout in the ASIC field is equally profound.
In 2019, Marvell completed the acquisition of GlobalFoundries' ASIC business, Avera, laying the foundation for its custom chip business. With the growth in AI computing demand, Marvell's custom chip (ASIC) business has become a core growth driver.
On March 31, 2026, NVIDIA announced a $2 billion investment in Marvell, establishing a strategic partnership through NVLink Fusion technology, connecting Marvell to NVIDIA's AI Factory and AI-RAN ecosystem. Marvell will provide custom XPUs and NVLink Fusion-compatible networking solutions, jointly developing next-generation infrastructure and silicon photonics technology.
On December 2, 2025, Marvell announced the acquisition of optical interconnect technology company Celestial AI for approximately $3.25 billion, with the transaction completed in Q1 2026. Celestial AI's Photonic Fabric technology offers double the energy efficiency of copper interconnects and can support high-bandwidth, low-latency connections for large-scale AI systems. Marvell also launched the 1.6T series of optical DSP products, expanding it to COLORZ 1600 in March 2026, providing end-to-end optical interconnect solutions for AI data centers.
According to financial reports, Marvell's total revenue for fiscal year 2026 was $8.195 billion, a year-on-year increase of 42%; data center revenue, including ASICs, reached $6.1 billion, accounting for about 74% of total revenue. In fiscal year 2024, data center revenue accounted for only about 40%. This means that in just about two years, Marvell's business structure has undergone a significant shift.
It is understood that Marvell's largest ASIC customer is Amazon AWS (contributing core IP for the Trainium chip); Google, Microsoft, and Meta are all confirmed partners: Google jointly developed the Axion Arm CPU with Marvell, Microsoft's next-generation AI accelerator Maia was deeply involved in design by Marvell, and Meta is cooperating on custom AI XPUs. Marvell claims to have secured AI ASIC design orders at over 20 customers.
The core difference from Broadcom lies in the service model: Broadcom provides end-to-end solutions deeply integrated with its own networking product portfolio, making customers highly dependent on its ecosystem once adopted; Marvell offers more flexible on-demand modular solutions, more suitable for customers wishing to control their own architecture.
Marvell CEO Matt Murphy said: "High-speed interconnects and optical interconnects are becoming increasingly important in AI scaling. Marvell combines ASIC customization with high-speed interconnect technology, providing customers with high-performance connectivity and ASIC solutions, aiming to increase the proportion of AI-related business revenue to over 50% and become a key player in the AI infrastructure field."
It is noteworthy that the cooperation between Broadcom, Marvell, and companies like OpenAI and Meta reveals a deeper industrial logic: for top AI companies, the primary consideration for self-developed ASICs may not be cost, but supply chain security and architectural autonomy. "Mastering chip definition power" has become a clear strategic dividing line.
In this game, cost is only the surface incentive; architectural sovereignty is the deeper gravitational center.
Looking at the ASIC landscape: First, mobile chip manufacturers, leveraging profound SoC design experience, have completed cross-domain transformation from edge to center. MediaTek's story is about the cross-domain reuse of system integration capabilities, while Qualcomm's is about capital M&A and顺势 transformation. Both paths lead to the same conclusion—the player structure in the ASIC field is undergoing generational change. Second, the moats of traditional ASIC twin giants are far deeper and wider than anticipated. Third, cloud vendors themselves are accelerating from being purchasers to self-developers, fundamentally rewriting the bargaining structure of the industry chain.
The Rise of Chinese Forces in the ASIC Wave
More intriguing is that the participants in this ASIC feast are not only Western giants. Within the mainland semiconductor industry chain, independent IC design service providers represented by VeriSilicon Microelectronics and ASR (Awinic) are becoming an unignorable new force.
VeriSilicon: The "Shovel Seller" of AI ASICs
2025 was a year of qualitative change for VeriSilicon. Annual newly signed order amount reached RMB 5.96 billion, doubling year-on-year with a growth of 103.41%. Among these, orders related to AI computing power already accounted for over 73%, with orders in the data processing field exceeding 50%, primarily from cloud-side AI ASICs and IP. By year-end, VeriSilicon's orders on hand reached RMB 5.075 billion, maintaining a high level for nine consecutive quarters, with over 80% expected to convert into revenue within one year.
These figures themselves are dazzling enough, but in April 2026, the order announcement released by VeriSilicon shocked the industry: newly signed orders from January to April amounted to RMB 8.24 billion, with AI computing power-related orders accounting for 91.37%, and an additional RMB 3.724 billion in AI ASIC orders added within just 9 days. Q1 financial report shows VeriSilicon's revenue at RMB 836 million, a year-on-year increase of 114.47%, with one-stop chip customization business growing 145.90% year-on-year.
This data strongly validates the continued explosion of global AI ASIC demand from a commercial perspective and provides clear and expected order support for VeriSilicon's subsequent performance growth.
VeriSilicon's core competitiveness lies in its full-stack ASIC service capabilities. From IP licensing to chip design and mass production business, VeriSilicon provides one-stop solutions, focusing on cloud-side AI ASICs. Its customers cover global leading cloud vendors, while also actively deploying in emerging endpoint scenarios like AI glasses and AI toys. More interestingly, the ultra-low-power Coral NPU IP (based on RISC-V instruction set) co-developed by VeriSilicon and Google has opened a channel for dedicated ASICs in endpoint AI scenarios.
VeriSilicon CEO Wayne Dai said during the Q1 2026 earnings call: "The AI ASIC market is exploding, and customer demand far exceeds expectations. Leveraging 20 years of IP accumulation and chip design experience, VeriSilicon has become the preferred ASIC customization partner for global cloud vendors and AI companies. The proportion of AI-related orders exceeding 90% in 2026 marks VeriSilicon's successful transformation into an AI computing power infrastructure service provider."
It can be seen that VeriSilicon's role is evolving from a pure IP supplier to an end-to-end AI ASIC platform enterprise, playing a hub role as an "enabler" in the industry chain.
ASR (Awinic): Cellular Baseband Giant Tapping into a Second Growth Curve
As a veteran player in the communication chip field, ASR (Awinic) has found its second growth curve in the ASIC track.
Since the second half of 2024, custom demand in directions like smart wearables, endpoint AI, and RISC-V chips has continued to rise. ASR has undertaken multiple custom projects using advanced process technologies, with a full order book. In 2025, ASR's revenue grew 12.73% to RMB 3.817 billion, and losses narrowed significantly by over RMB 300 million.
In Q1 2026, ASR's ASIC customization business revenue was RMB 188 million, a year-on-year increase of 73%, accounting for 23% of total revenue. To accelerate its layout, ASR established a wholly-owned subsidiary for ASIC business, tilting 20% of R&D resources towards the customization business, covering AI cloud-side, endpoint, wearable, and RISC-V fields.
ASR's differentiated advantage lies in its system-level ASIC solution capabilities. With years of technological accumulation in the baseband SoC chip field, ASR can provide full-process services from chip design to system optimization, leveraging mature IP libraries and supply chain channels to help customers shorten development cycles and reduce costs.
Comparing the two, a common characteristic of VeriSilicon and ASR is that they do not rely on a single customer or project but embed themselves into the larger AI industry ecosystem by virtue of systematic IP portfolios and customization capabilities, playing the role of "shovel sellers."
In the market atmosphere of the AI gold rush, those who sell shovels often earn the steadiest profits. VeriSilicon and ASR are establishing their golden window between the identities of "shovel seller" and "enabler" for AI ASICs, leveraging China's rich industry chain resources and application scenarios to strive for greater voice in the global AI chip competition.
From Self-Use to External Sales: The Underlying Restructuring of the AI Industry Chain
The deep-seated characteristics of the ASIC golden era lie not only in what has grown but also in what has changed.
Among these, a dramatic signal appeared at the end of 2025. According to reports, Google was negotiating with Meta to directly sell its self-developed TPU chips. Once this deal, worth billions of dollars, lands, it will mark TPU's transition from Google's internal private tool to commercial external sales—Meta plans to rent TPU computing power from Google Cloud in 2026 and spend directly on purchasing hardware for deployment in its own data centers in 2027.
Against the backdrop of NVIDIA GPUs long holding over 90% market share, the substance of this cooperation is that cloud vendors are voting with real money to build an open computing power supply chain of "self-developed + external procurement" to break the path dependence on a single supplier.
Meanwhile, the mature ASIC design service ecosystem represented by Broadcom, Marvell, MediaTek, etc., has formed a highly specialized division of labor closed loop: CSPs define specifications, chip makers handle design, and TSMC is responsible for advanced packaging. This refined foundry system makes it possible for any large enterprise with sufficient computing power demand, whether OpenAI, Apple, or emerging players still in planning, to become the master of the next self-developed ASIC.
The global AI chip market is moving from NVIDIA's monopoly towards genuine contention among a hundred schools of thought.
The other side of this transformation is the comprehensive and synergistic upgrade of underlying industry chain technologies.
The ASIC boom driven by AI places higher-order demands on computing architecture. TSMC's monthly CoWoS advanced packaging capacity is expected to expand significantly from about 65,000 to 70,000 wafers at the end of 2025 to 120,000 to 130,000 wafers by the end of 2026, yet even this cannot fully meet the strong customer demand.
Simultaneously, Broadcom launched the industry's first 3.5D XDSiP face-to-face computing SoC platform, supporting independent scaling of computing, storage, and I/O in a compact form factor to meet the massive demands of gigawatt-level AI computing power clusters.
The synchronous evolution of these underlying technologies indicates that the rise of ASICs is not an isolated event but is embedded in the evolution of the entire industry chain from advanced processes and advanced packaging to high-speed interconnects—the competitive focus of AI infrastructure has completely shifted from "competing on single-point computing power" to competing on system architecture efficiency.
Challenges and Games Coexist in ASICs
Behind the glory, any trend has its clear and sober other side, and ASICs are no exception.
Industry practitioners have indicated to the author: "Development costs and tape-out risks are the Sword of Damocles hanging over every ASIC player's head." An AI ASIC chip using advanced processes, from design to tape-out, easily costs hundreds of millions of dollars. Once there is an error in technical path judgment or demand pace falls short of expectations, investments of billions of dollars may face abortion risk.
This is evident from the financial reports of companies like Broadcom and Marvell; the upfront heavy-investment nature of the custom ASIC business does impose a certain structural drag on overall gross margins—a pressure not negligible in the short term.
The moat of the software ecosystem is the most stubborn barrier ASICs face.
As is well known, NVIDIA's true moat has never been just hardware but the massive software stack built over more than a decade of polishing CUDA: millions of developers, countless accumulated libraries and frameworks, and an operator ecosystem optimized over years. Although AWS announced that the next-generation Trainium will be compatible with NVIDIA's NVLink interconnect technology, attempting to thin this barrier by entering the mainstream ecosystem, the path for the ASIC ecosystem to catch up to the maturity level rivaling CUDA is still long.
Another structural constraint cannot be ignored: the global AI chip orders' concentrated dependence on TSMC's CoWoS advanced packaging. Although TSMC is expanding capacity at an unprecedented speed, amid simultaneous order grabs by various giants, the congestion risk in production scheduling remains significant. Coupled with the impact of geopolitical and supply chain uncertainties, this is not a variable that can be easily overlooked.
Furthermore, a deeper test lies in the classic trade-off between full customization and programmability/flexibility. When ASIC shipments are expected to surpass commercial GPUs in actual quantity by 2028, what will be tested is no longer crude scaling ability, but how to balance dedicated extreme efficiency with general-purpose elastic adaptability—the former is the reason for ASIC's existence, the latter is an advantage the market is unwilling to give up.
For the current industry consensus, perhaps there is no perfect answer; the final direction the industry chooses can only be left to the market and time to verify.
In Conclusion
Looking back from 2026, a more three-dimensional judgment is becoming clear: the endgame is not ASICs completely replacing GPUs, but both finding their irreplaceable ecological niches within a new coexisting landscape.
Synthesizing predictions from multiple institutions, the competitive landscape of the AI accelerator market is moving towards a specialized division of labor of "training relies on GPUs, inference relies on ASICs," or towards mixed clusters of ASICs and GPUs at larger scales.
It is also worth noting that multiple key variables will determine how far the ASIC narrative can go in the AI era.
- The Evolution Direction of AI Workloads: The continuity of the Transformer architecture directly relates to the return ceiling of ASIC-specific designs—every dramatic change in architecture is a potential fissure in the ASIC investment logic.
- The Degree of Ecosystem Openness from Cloud Vendors: The signal of Google selling TPUs to Meta is extremely important. If CSP self-developed chips transition comprehensively from internal cost reduction to external output, ASICs will upgrade from a cost story to a true market story.
- The Innovation Pace of System Architecture: The full-stack optimization capability from chip to rack, from computing power to interconnect, is replacing single-chip TOPS as the new core benchmark for industrial competition. Whoever can first find the optimal solution in the comprehensive matrix of CoWoS capacity, 3.5D packaging, and high-speed SerDes will lock in the leading position for the next leg of the golden era.
The golden era of ASICs is essentially a movement about the "democratization" of AI computing power.
Whether it's MediaTek's cross-border advance, Qualcomm's fightback from a difficult position, Broadcom and Marvell's in-depth layouts, or the breakthroughs of VeriSilicon and ASR, the forces collectively paint the real backdrop of this diverse and symbiotic era.
It shifts the definition power of computing from the concentrated hands of a single chip giant, beginning to return to cloud vendors, equipment manufacturers, and even end-users across industries. It heralds the loosening of an old ecosystem and the arrival of a new logic: on the question of what chips to use, the industry finally has more choices.
This article is from the WeChat public account "Semiconductor Industry Observation" (ID: icbank), author: L Chenguang
